SystemVerilog Announcements

• SystemVerilog reference verification methodology: RTL (05/01/2006)
• SystemVerilog reference verification methodology: Introduction (03/27/2006)
• Synopsys Delivers First Complete SystemVerilog Design and Verification Flow (03/20/2006)
• Synopsys Announces EDA Industry’s First Verification IP Library for SystemVerilog with Methodology Support (03/20/2006)
• Power analysis tool suite adds SystemVerilog support (02/28/2006)
• 16 Synopsys Technologists Recognized for Leadership in Creation of SystemVerilog Standard (02/22/2006)
• JasperGold Verification System 4.1 Delivers Systematic Formal Verification to the SystemVerilog Community (02/22/2006)
• French firm adds SystemVerilog assertion support to debug tool
• IEEE Recognizes Mentor Graphics’ Dennis Brophy and Dave Rich for Contributions to SystemVerilog Standard (01/20/2006)
• Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization (07/26/2006)
• ARM-Synopsys Verification Methodology Manual for SystemVerilog Endorsed by Leading Japanese Semiconductor Companies (01/25/2006)
• IEEE Approves SystemVerilog and Verilog Standards (11/09/2005)
• Accellera Applauds IEEE 1800 SystemVerilog Standard Approval (11/09/2005)
• Quote Sheet for above press release (11/09/2005)
• Aldec Releases Active-HDL 7.1 with New Simulation Technology and SystemVerilog Support (10/31/05)
• Cadence Provides Powerful Low-Risk SystemVerilog Verification from Plan to Closure (10/24/05)
• Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench Automation (09/26/05)
• Springer Publishes ARM-Synopsys Verification Methodology Manual For SystemVerilog (09/21/2005)
• Synopsys Announces Source-Code License for SystemVerilog Verification Library (09/21/05)
• Springer Publishes '”A Practical Guide for SystemVerilog Assertions (06/08/05)
• Mentor Graphics Attacks Verification Bottlenecks With New Questa Verification Products Supports SystemVerilog, VHDL, PSL,and SystemC (05/16/05)
• AXIOM Introduces Industry's Fastest multi-CPU SystemVerilog Simulator (05/16/05)
• Mentor Graphics Donation of SystemVerilog Assertion (SVA) Version of Open Verification Library Accepted by Accellera (03/30/05)
• Cadence donates technology to IEEE to enhance SystemVerilog usability (02/14/05)
• Development of New IEEE VerilogR Standard Reaches Major Milestone (02/14/05)
• New SystemVerilog Book Helps Engineers Master Assertion-Based Verification (01/26/05)

SystemVerilog Coverage

• Language standards from IEEE open choices (12/19/2005)
• IEEE approves SystemVerilog, revision of Verilog (11/09/2005)
• Verilog's inventor nabs EDA's Kaufman award (11/04/05)
• SystemVerilog verification manual published (09/21/05)
• A Tale of Two Languages: SystemC and SystemVerilog (06/01/05)
• Verification tool (VeriEZ) adds SystemVerilog support (05/26/05)
• New simulation capabilities advance SystemVerilog (05/16/05)
• IEEE SystemVerilog heads for balloting (notice the new web folder "latest") (2/14/05)

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